Special Session on:
Multi-Core and Many-Core systems for EMbedded Computing - (MC)3
Recent trends in the microprocessor industry have important ramifications for the design of the next generation of embedded computing systems. By increasing number of cores, it is possible to improve the performance while keeping the power consumption unchanged. This trend has reached the deployment stage in embedded systems ranging from small ultramobile devices to large telecommunication servers. It is also expected that the number of cores in these systems rises dramatically in the near future.
Although these systems can potentially provide significant performance benefits, in practice, there are technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. Therefore, it is necessary to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth.
This special session addresses all aspects of multi-core and many-core embedded systems design. It presents new ideas in the multi-core field such as theory and modeling, scalable and fault tolerant design approaches and frameworks, algorithms, software, tools and applications, analysis and comparison, design techniques and emerging implementations.
Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics:
- Design space exploration and design methodology for embedded multi-core and many-core systems,
- Specification and Formal modeling of embedded multi-core and many-core systems,
- Multi-core/many-core embedded system design challenges,
- Parallel programming and software for embedded multi-core and many-core systems,
- Memory management,
- 3D architectures, integration and synthesis for embedded multi-core and many-core systems,
- On-chip communication architectures and networks-on-chip for embedded systems,
- Heterogeneous multi-core and many-core architectures,
- Hardware/software co-design,
- Simulation, validation and verification,
- QoS management and performance analysis,
- Multi-core and many-core cyber-physical systems,
- Programming languages and compilers,
- Thermal-, energy-, and power-aware architectures,
- Monitoring and reconfiguration,
- System prototyping,
- Test and fault tolerance,
- Industrial practices and case studies,
Important dates
Paper submission:Acceptance notification:
Camera ready due: 20th Nov 2014
Registration due: 20th Nov. 2014
Conference: 4th - 6th Mar 2015
Session Organizers
- Hannu Tenhunen, KTH, Sweden
- Axel Jantsch, KTH, Sweden
- Pasi Liljeberg, Universiy of Turku, Finland
- Amir Rahmani, Universiy of Turku, Finland
Programme Committee:
- José L. Ayala, Complutense University of Madrid, Spain
- Peeter Ellervee, Tallinn University of Technology, Estonia
- Juha Plosila, University of Turku, Finland
- Waltenegus Dargie, Technical University of Dresden, Germany
- Zhonghai Lu, Royal Institute of Technology, Sweden
- Martti Forsell, VTT & University of Oulu, Finland
- Jari Nurmi, Tampere University of Technology, Finland
- Leandro Soares Indrusiak, University of York, UK
- Jouni Isoaho, University of Turku, Finland
- Dinesh Pamunuwa, Bristol University, UK
- Mohamed Bakhouya, Aalto University, Finland
- Zhiyi Yu, Fudan University, China
- Sébastien Lafond, Åbo Akademi, Finland
- Seppo Virtanen, University of Turku, Finland
- Haoyuan Ying, Darmstadt University of Technology, Germany
- Leonidas Tsiopoulos, Åbo Akademi, Finland
- Johan Lilius, Åbo Akademi, Finland
- Tiberiu Seceleanu, ABB Corporate Research, Sweden
- Tomi Westerlund, University of Turku, Finland
- Gert Jervan, Tallinn University of Technology, Estonia
- Ville Leppänen, University of Turku, Finland
- Shashi Kumar, Jönköping University, Sweden
- Ethiopia Nigussie, University of Turku, Finland
- Gabriel Marchesan Almeida, Karlsruhe University, Germany
- Liang Guang, University of Turku, Finland
- Jerker Björkqvist, Åbo Akademi, Finland
Submission guidelines
Prospective authors should submit a full paper not exceeding 8 pages in length (and in the Conference proceedings format – double column, 10pt) including a 150-200 word abstract. To facilitate a double blind reviewing process, the first page of the paper should contain only the title and abstract and reference entries to the author’s own work should be substituted with the string “omitted for blind review”.
Papers submitted for the special session must be submitted through the conference submission system with an indication of the name of the special session. Papers must adhere to the formatting rules of the conference and will undergo the same review process as papers submitted to the main track.
Publication
All accepted papers will be included in the same volume, published by the Conference Publishing Services (CPS). The Final Paper Preparation and Submission Instructions will be published after the notification of acceptance. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be submitted to IEEE explore, CSDL, and for indexing among others to DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.
Authors of selected papers will be invited to submit extended article versions to one of the ISI-indexed high-quality journals.
Past sessions
- “Multi-Core and Many-Core systems for EMbedded Computing” special session at PDP 2014
- “Dynamic and Reliable Multicore Systems” special session at PDP 2013
Contacts
| H. Tenhunen | A. Jantsch | P. Liljeberg | A. Rahmani | |||
|
KTH, Sweden |
KTH, Sweden |
University of Turku, Finland |
University of Turku, Finland |